1. Field of the Invention
Embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a nonvolatile memory device capable of minimizing an occurrence of program interference between adjacent cells.
2. Description of the Related Art
In a nonvolatile memory device such as a NAND flash memory, a program cell threshold voltage (Vt) distribution type is an important factor that dominates a performance of devices.
Among phenomena that have the greatest affect on the program cell Vt distribution type between adjacent cells, there is a program interference phenomenon between adjacent cells. The program interference phenomenon may cause fluctuation in Vt values of cells due to a coupling effect between adjacent cells.
FIG. 1 is a diagram illustrating Vt distributions of cells for explaining an initial program operation of a NAND flash memory.
Referring to FIG. 1, when forming level distributions divided into ‘ERASE’, ‘PV1’, ‘PV2’, and ‘PV3’ so as to generate Vt distributions of 2-bit multi-level cells in a NAND flash memory, a scheme of sequentially programming all the level distributions by starting from ‘ERASE’ is performed. This sequential programming may cause the amount of interference suffered when adjacent cells are programmed to increase as the programming sequence is executed. This interference may greatly fluctuate the level distributions of the Vt between the adjacent cells.
FIG. 2 is a diagram illustrating the Vt distributions of cells for explaining program operations proposed so as to solve problems that may occur during an initial program operation of the NAND flash memory illustrated in FIG. 1.
Referring to FIG. 2, when forming the level distributions divided into ‘ERASE’, ‘PV1’, ‘PV2’, and ‘PV3’ so as to generate the Vt distributions of the 2-bit multi-level cells in the NAND flash memory, a scheme of first forming least significant bit (‘LSB’) distribution in the ‘ERASE’ and then, forming ‘PV1’ distribution in the ‘ERASE’ or the ‘PV1’ distribution or the ‘PV3’ distribution in the ‘LSB’ is performed, such that the amount of interference suffering when the adjacent cells are programmed may be further reduced as compared with the program scheme illustrated in FIG. 1, thereby making the fluctuation in the level distributions of the Vt between the adjacent cells relatively small.
However, as a cell size of the NAND flash memory is further reduced, it is difficult to solve the interference phenomenon affecting the adjacent cells just by changing the program operation scheme as illustrated in FIG. 2.
FIG. 3A is a block diagram for explaining a scheme of controlling a program operation sequence between adjacent cells according to an even-odd bit-line (EOBL) program operation so as to minimize an influence of the interference phenomenon on Vt distributions between the adjacent cells.
FIG. 3B is a block diagram for explaining problems with the scheme of controlling the program operation sequence between the adjacent cells according to the even-odd bit-line (EOBL) program operation illustrated in FIG. 3A.
FIG. 4 is a block diagram for explaining the scheme of controlling the program operation sequence between adjacent cells according to an all bit-line (ABL) program operation so as to minimize an influence of the interference phenomenon on Vt distributions between the adjacent cells.
Referring to FIG. 3A, in order to reduce the interference phenomenon between adjacent cells, the LSB program operation is performed on all the adjacent cells, followed by performing an most significant bit (MSB) program operation on specific cells according to the even-odd bit-line (EOBL) program operation, thereby minimizing the interference phenomenon affecting specific cells.
Thus, the LSB program operation is performed in all the adjacent cells followed by the MSB program operation. Because the program operations are repeatedly performed in adjacent cells, fluctuations in the Vt distributions are large due to the interference phenomenon affecting the specific cells.
That is, as illustrated in FIG. 3B, when expanding the structure of FIG. 3A, the LSB program operation is performed in all the adjacent cells and then the MSB program operation is performed. The program operations, however, may be performed a maximum of three times in cells adjacent to the specific cells. When considering the recent trend of reducing cell size, fluctuations in the Vt of the specific cells due to the interference phenomenon affecting the specific cells, may cause wrong data to be programmed in the specific cells.
In order to solve problems with the scheme of controlling the program operation sequence between adjacent cells according to the even-old bit-line (EOBL) program operation illustrated in FIGS. 3A and 3B, the all bit-line (ABL) program operation scheme simultaneously performing the program operations of all the adjacent memory cells in a word line direction as illustrated in FIG. 4 has been proposed. However, the above-mentioned ABL program operation is a scheme in which page buffers are independently provided for each bit line and therefore, the occupied area is significantly large, which is not an appropriate scheme for solving problems of the type of controlling the program operation sequence between the adjacent cells illustrated in FIGS. 3A and 3B.